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Topics: INTEL processor AMD MOTOROLA NEC CPU history evolution DEC
The evolution of processors.
Part 4: RISC architecture and industry development in the 1990s
25.07.2014
Oleg Kolenchenko, info@ferra.ru
Print version
In the previous parts of this series of articles, we talked exclusively about CISC processors.
In this part of the material, we will follow how the development of the RISC architecture began.
We will also pay attention to the last decade of the XX century and the nascent rivalry between AMD and Intel.
Table of contents
Creating a RISC architecture MIPS processors SPARC processors ARM processors PowerPC processors DEC Alpha processors Intel P5 Architecture AMD K5 Architecture Intel P6 Architecture AMD K6 Architecture Instead of concluding
Previous parts:
Part 1: The 8 bit Era;
Part 2: The 16 bit Era;
Part 3: 32 bit processors in the second half of the 1980s.
Creating a RISC architecture
As has been repeatedly mentioned, all x86 processors, Motorola solutions and the vast majority of crystals released in the 1980s had the CISC (Complex Instruction Set Computing) architecture.
The combination of all the features has led to the fact that the chips have become not only complex and expensive to produce, but also reached their performance ceiling.
To further increase the speed, it was necessary to increase the number of transistors, but the mastered technological standards did not allow creating more complex solutions.
Intel faced this when releasing the i486 family.
To improve performance, they made changes to the processor architecture, adding cache memory, multipliers and pipelines.
the processor, when executing small programs, was on average twice as fast as the VAX 11/780 and about four times more productive than the Zilog Z8000" stone".
RISC II differed from its predecessor in a large number of instructions: 39 versus 32.
He was faster.
Its advantage over the VAX processor reached 200%, and the Motorola 68000 was about four times slower in some programs.
It should be noted that Berkeley RISC was part of a large project called VLSI.
This also included the Stanford University MIPS project, which started in 1981.
MIPS processors
The head of the MIPS project was Stanford University scientist John Hennessy.
As in the case of Berkeley RISC, the startup's task was to research and create a processor that would use a pipeline and a reduced set of commands.
The architecture of MIPS solutions also provided for the presence of auxiliary blocks in the crystal: for example, modules for working with memory, an integer ALU (arithmetic logic device) and command decoders.
The difference between the MIPS plan and the Berkeley RISC was the use of an extended conveyor.
The RISC architecture, in principle, assumes the use of a pipeline, but Hennessy went further and proposed to lengthen the pipeline in the processor as much as possible, that is, to "split" the execution of a single operation even more.
This approach opened up even greater scope for increasing the clock frequency.
At the same time, the lengthening of the pipeline provided more efficient parallelization of command execution.
At that time, parallelization was a distinctive feature of the RISC architecture, since this function was not implemented in any CISC processor until the appearance of pipelines in them.
For example, in MIPS, as well as in RISC, the execution of one command could not yet be completed when the other one began to be executed.
In CISC processors, to start the execution of one instruction, it was necessary that the processing of the other was completed.
John Hennessy creator of the MIPS architecture, and now president of Stanford University
Image source
The original specification of MIPS processors did not provide support for such elementary operations as multiplication and division.
This was done on purpose.
Thus, the developers wanted to get rid of the need to use so called pipeline locks.
The blocking itself was a suspension of the pipeline in cases when an operation at a certain stage of the pipeline cannot be performed in one clock cycle.
Nevertheless, the first implementations of the MIPS architecture worked with locks and even supported multiplication and division operations.
It took some time before the original idea was implemented in the processors.
In 1984, Hennessy left Stanford University and founded MIPS Computer Systems, which started producing processors with the same architecture.
A year later, the company's first product was released — the 32 bit "stone" R2000.
It became the first commercially available RISC model in history.
In 1988, a next generation processor called the R3000 appeared.
In comparison with the R2000, it received support for multiprocessing and a cache of instructions and data.
"Three thousandth" was commercially successful.
The processor was used in server systems and workstations of such companies as Silicon Graphics, DEC, Seiko Epson and many others.
Plus, the R3000 has become the heart of the Sony PlayStation game console.
MIPS R3000 processor
Image source
It took three years to develop the next generation of MIPS processors.
The R4000 processor was introduced in 1991.
It received a 64 bit architecture, a built in coprocessor and worked at a higher clock frequency than its predecessors.
So, the minimum frequency of the R4000 was 100 MHz.
The amount of instruction and data cache memory was 8 KB each.
Two years later, a modified version of the processor with the R4400 index was presented.
The new crystal had a doubled cache and supported a larger cache memory of the second level.
In addition, numerous errors were fixed when working in 64 bit mode.
Surprisingly, despite the commercial success of its processors, MIPS experienced financial difficulties and was eventually bought by SGI and renamed MIPS Technologies.
After that, licenses for the production of clones began to be issued to third party companies.
So, the company QED (Quantum Effects Devices) created inexpensive MIPS processors that were used in Cisco routers.
And NEC was engaged in the production of the VR4300 "stone", which was" registered " in the Nintendo 64 game console.
The NEC VR4300 processor was used in the Nintendo 64 console
Image source
In 1994, the R8000 processor appeared.
It became the first MIPS solution with a superscalar architecture, which implies parallel execution of commands, provided that the execution of one command does not depend on the result of another.
For example, the R8000 could process up to four instructions per clock cycle.
In January 1996, MIPS introduced a next generation processor called the R10000.
The "Ten Thousandth" used the same superscalar architecture as the R8000, and, in fact, was a modified version of its predecessor.
The processor also had a cache of instructions and data of 32 KB each and operated at a frequency of 175 MHz or 195 MHz.
In 1997, there was even a version of the chip with a frequency of 250 MHz.
But even with the parameter of 195 MHz, the R10000 was one of the fastest processors of that time.
The R10000 processor, manufactured by Toshiba
Image source
Unfortunately, after the launch of R10000, SGI abandoned the MIPS architecture.
All subsequent crystals were based on the core of the "ten thousandth" and did not have any fundamental differences in comparison with it.
For example, the R12000 processor, introduced in 1998, received an additional stage in the pipeline and improved work with instruction queues.
Its clock frequency was 270 MHz, 300 MHz or 360 MHz.
After the R12000, two more generations of MIPS processors were released: R14000 and R16000.
They received support for faster system buses, increased frequencies and a larger cache memory.
For example, the R16000 could operate at a frequency of 700 MHz and supported 64 Kbytes of instruction and data cache memory.
After that, MIPS started selling licenses for the 32 bit and 64 bit MIPS32 and MIPS64 architectures.
SPARC Processors
Sun Microsystems also decided to develop an architecture — SPARC (Scalable Processor ARChitecture).
So, the engineers drew inspiration from the Berkeley RISC project.
And David Patterson himself was even involved in the project as a consultant.
However, as a result, SPARC more closely resembled the MIPS architecture.
For example, the platform's instruction set also lacked multiplication and division instructions.
A feature of the SPARC architecture was the use of a register window, with the help of which the process of calling functions in programs was slightly changed.
Usually, when calling programs, the processor remembered its state (that is, it remembered the state of some general and special purpose registers), went to the execution of the function, and then returned to its original state before calling the function.
And in SPARC processors, when calling a function, the necessary data was written to the end of the register window, and the register window itself was moved through the file so that the data was at the beginning of the window.
This approach in theory provided a higher speed of work.
The SPARC V7 processor, manufactured by Fujitsu
Image source
The first version of the architecture was called SPARC V7.
The processor of the same name was produced on its basis until 1992.
Then the next generation of the architecture appeared — SPARC V8.
It has not undergone any drastic changes.
The key differences were the addition of multiplication and division operations,as well as improved execution of floating point arithmetic.
Like SPARC V7, SPARC V8 remained a 32 bit architecture, on the basis of which the microSPARC processor was created.
It belonged to the Low End segment and was used in small workstations and embedded systems.
Improved clones were also released by Texas Instruments and Fujitsu.
A more productive solution was the SuperSPARC processor.
The whole organization SPARC Architecture Committee, which, in addition to Sun itself, included such companies as Texas Instruments, Fujitsu, Philips and many others, was already working on the creation of the next generation of architecture named SPARC V9.
The platform was expanded to 64 bits and was superscalar with a 9 stage pipeline.
SPARC V9 provided for the use of the first level cache memory, divided into instructions and data of 16 KB each, as well as the second level with a capacity of 512-4096 KB.
The implementation of the architecture was the UltraSPARC processor with a frequency of 143-200 MHz.
UltraSPARC II processor
Image source
UltraSPARC was not the only processor with the SPARC V9 architecture.
In 1997, the UltraSPARC II was introduced.
ARM processors
The history of the now popular ARM processors, or rather the ARM architecture itself, begins with Acorn Computers and its BBC Micro computer.
It used the MOS Technology 6502" stone", but its performance was not enough to create a next generation desktop.
For various reasons, other available processors also did not fit the requirements of Acorn, so the company thought about creating its own chip.
After studying various architectures, Acorn engineers took RISC processors as a basis and all that the same crystal MOS Technology 6502.
BBC Micro Computer
Image source
For example, the memory access architecture and instruction set were borrowed from the MOS processor.
Each instruction was supplemented with a special four bit condition code.
Depending on the value of the code (true or false), the instruction could be executed or not executed.
This made it possible to reduce the number of transitions when performing operations that negatively affected the performance of the pipeline architecture.
The developers also included teams that performed several elementary operations in the initial revision of the architecture.
In short, we have slightly deviated from the RISC rules.
However, in the end, this only improved the performance of the processor.
The development of the architecture was completed in 1985 with the creation of the ARM processor.
The first commercial variants appeared in 1986 and were called ARM2.
Compared to CISC processors, the ARM2 was very simple — it contained only 30,000 transistors.
At the same time, it consumed very little energy and at the same time was quite productive.
A little later, ARM processors appeared, in which 4 Kbytes of cache memory were added, which further increased the performance of the crystals.
ARM2 Processor
Image source
By the end of the 1980s, Acorn was no longer developing the ARM architecture alone – Apple joined it.
In this regard, the division that was directly engaged in ARM processors was transformed into a separate company – Advanced RISC Machines.
The first product of the new company was the ARM6 processor core and the ARM610 processor, which was used in one of the world's first Apple Newton PDAs.
However, ARM processors could no longer compete with CISC solutions in terms of performance, and MIPS processors dominated the RISC segment.
Then ARM went a different way.
The company began to position ARM6 as an embedded core that any third party manufacturer could use in their processors for little money.
This policy has borne fruit, and the ARM core has become very popular, and the company itself has become commercially successful.
Together with DEC, an architecture was developed for more productive ARM solutions called StrongARM, which was a classic scalar architecture with a 5 stage pipeline.
The architecture had memory management blocks and supported a cache of instructions and data of 16 KB each.
The first processor based on StrongARM — SA 110 - was introduced in February 1996.
It worked at clock frequencies of 100 MHz, 160 MHz or 200 MHz.
The "stone" was used in the Apple MessagePad 2000, as well as the Acorn Computer Risc PC and Eidos Optima systems.
Throughout 1996, the SA 110 remained the most productive mobile processor.
The Apple MessagePad 2000 used an SA 110 processor
Image source
In 1997, the rights to the StrongARM architecture were sold to Intel, which began developing the next generation of the platform.
In 2000, it was introduced, but the architecture (or rather the implementation of the architecture) had a different name Xscale.
The platform has received many changes.
For example, the length of the conveyor was increased to 8 stages.
The amount of cache memory for both instructions and data has increased to 32 KB.
XScale was used in devices such as RIM Blackberry, Dell Axim, Motorola A780 mobile phone and other devices.
PowerPC Processors
To be more precise, IBM was the first company to start developing the RISC architecture.
Back in 1974, the development of the IBM 801 processor started, which laid the first foundations for this platform.
And the Berkeley RISC project finally formed the architecture.
In the early 80s, some IBM processors for embedded systems used the 801 architecture.
The processor based on it was also "registered" in the IBM 9370 computer.
In 1985, IBM began developing the next generation RISC architecture.
The project was named America Project.
The development of the processor and the instruction set for it ended in 1990.
The crystal itself was named POWER1 and was used in IBM servers and workstations.
It had a fairly high level of performance, but had a multi chip layout and consisted of 11 different chips.
In 1992, IBM introduced a budget version of the POWER1 processor, which fit into a single chip.
The POWER1 processor.
Even, rather, a chipset
Image source
In 1993, the second generation of the POWER2 architecture was introduced.
One additional block of arithmetic and logical operations and floating point calculations was added to it.
The set of commands was also expanded: for example, the operation of calculating the square root of a number at the hardware level was added.
The processor clock frequency ranged from 55 MHz to 71 MHz, and the cache memory of data and instructions was 256 KB and 32 KB, respectively.
Like its predecessor, the new processor had a multi chip layout.
But in May 1994, a single chip version was also released.
However, even before the release of POWER2, IBM, together with Apple and Motorola, formed the AIM alliance and agreed to create an improved architecture based on POWER.
All three companies won, having received one of the fastest RISC processors on the market.
The architecture developed jointly was called PowerPC.
In addition to the basic set of functions of the POWER platform, support for working in two modes (big endian and little endian), new instructions for floating point calculations and backward compatibility with the 32 bit mode of operation for the 64 bit version of the architecture were added to it.
First generation PowerPC processor
Image source
Unlike other RISC architectures that occupied narrow market niches, PowerPC was positioned as a competitor to x86.
Its main purpose was personal computers.
For example, a PowerPC based processor was used for quite a long time in Apple Macintosh computers — until 2006.
The architecture competed on a par with x86 until 2001, but after that it could not keep up with Intel and AMD processors.
Despite this, PowerPC based processors were used in Sony PlayStation 3 and Microsoft Xbox 360 game consoles.
Sony's PlayStation 3 and Microsoft's Xbox 360 consoles run on a PowerPC processor
Image source
In the 90s, IBM managed to release the third generation of processors called POWER3, which, in fact, became an implementation of the 64 bit PowerPC architecture.
The chip was created with an eye to use in servers and workstations, but in the end, IBM RS/6000 systems became its main application.
DEC Alpha Processors
The DEC VAX architecture was hopelessly outdated and in the early 90s the company thought about developing its own RISC platform.
It became Alpha, released in 1994.
The first processor was the Alpha 21064, codenamed EV4.
This is a 64 bit superscalar crystal with a pipeline architecture.
That is, it had a classic RISC design.
The DEC processor was favorably distinguished by the smooth operation of all its blocks.
So, with an equal frequency with other "stones", the EV4 showed higher performance.
The external bus of the processor was 128 bit.
It had a 16 KB cache of data and instructions and was manufactured using CMOS 4 technology.
The clock frequency of the EV4 was 150 MHz or 200 MHz.
A little later, a modification called 21064A appeared, which could work at speeds up to 300 MHz, which provided the crystal with the title of the fastest processor of that time.
The main application of EV4 was servers and workstations.
Alpha 21064 processor
Image source
The Alpha 21064A remained DEC's top model until the release of the next generation of processors — 21164 (EV5).
It had two integer blocks and two floating point calculation modules.
In EV5, there were already three levels of cache memory: two were located directly in the processor, and the third was external.
The cache memory of the first level was divided into two parts: the data cache and the instruction cache of 8 KB each.
The volume of the second level cache memory was 96 Kbytes.
The processor clock frequency ranged from 266 MHz to 333 MHz.
The Alpha 21164 took over the palm from the Alpha 21064A and was the fastest processor before the release of the Pentium Pro.
However, DEC's response was not long in coming — the company released a more productive Alpha 21164A processor running at higher clock speeds (up to 666 MHz).
The processor was used in workstations and server computers of companies such as Digital, Network Appliance and Cray Research.
Alpha 21264 processor
Image source
In 1996, the next generation of DEC processors was introduced — Alpha 21264 (EV6).
The chip has received several important changes compared to previous models.
For example, it supported the extraordinary execution of instructions, which led to a complete reorganization of the kernel.
Integer blocks and load/save blocks were combined into a single Ebox module, and floating point calculation blocks were allocated to the Fbox module.
In addition to the blocks themselves, these units also contained register files.
The cache memory structure has again become two level — it replaced the three level cache organization in Alpha 21164.
The first level cache has preserved the memory separation for instructions and for data.
The volume of each part was 64 Kbytes.
As for the second level cache memory, its volume could be from 1 MB to 16 MB.
Plus, the processor has received support for: the number of branches.
Over time, more and more new versions of Alpha 21264 processors were released, in which, first of all, the clock frequency was increased.
The latest modification was the Alpha 21264E, which operated at a frequency of 1250 MHz.
Alas, the Alpha 21264 processor line became the last in the history of the "independent" DEC.
In early 1998, DEC was declared bankrupt, and it was absorbed by Compaq.
Intel P5 Architecture
Processors with the RISC architecture for the most part occupied their specialized niche, but x86 crystals continued to be used in desktop systems anyway.
Their development continued, albeit with some changes.
Despite the fact that Intel entered the RISC processor market with its i860 and i960 solutions, the main bet in the company was still made on x86 crystals.
The next generation of "stones" became the well known Pentium based on the P5 architecture, released in 1993.
A lot of work has been done.
First, P5 has become superscalar.
The architecture worked using two pipelines, each of which could perform two operations per clock cycle.
Secondly, the data bus became 64 bit, which made it possible to transfer twice as much data per cycle.
Third, the cache memory of data and instructions was divided into two separate blocks of 8 KB each.
In addition, a branch prediction block was added to the processor, and the floating point calculation module became more productive.
The first processors of the Pentium line worked at frequencies of 60 MHz or 66 MHz.
At the same time, a voltage of 5 V was required for their operation, so they were very hot.
Also, the first "stumps" became famous for the incorrect operation of the floating point calculation block, which in some cases gave an incorrect result when dividing numbers.
Therefore, Intel soon launched processors with the corrected P54C architecture.
Intel Pentium Processor
Image source
P54C has become a kind of work on errors.
The production of new processors was transferred to the 0.6 microns process technology.
The crystals themselves now worked with a voltage of 3.3 V, which allowed us to solve the problem with overheating.
As for the changes at the architecture level, a one — and a half multiplier was added to the P54C from now on, the processors worked at a higher frequency than the system bus.
The speed of the processors was 75 MHz, 90 MHz or 100 MHz.
The P54C was also installed in Socket 5 or Socket 7 connectors.
Unlike the P5, which only supported Socket 4.
The P54C architecture itself was updated again in 1995, when it was transferred to the 350 nm process technology.
This made it possible to reduce the power consumption of the crystals again, as well as to increase their clock frequency to 200 MHz.
Pentium MMX Processor
Image source
In 1996, the P5 received the latest update the P55C.
The key innovation was the support for the MMX (MultiMedia eXtension) command set, which significantly increased the performance of the architecture when working with multimedia.
And the new processors were called Pentium MMX.
However, this was not the only improvement of the platform.
The volume of the cache memory of the first level was increased to 32 Kbytes, and the production of Pentium MMX was transferred to 0.28 microns of the technological process.
This made it possible to increase the frequency of processors to 233 MHz.
This is the end of the development of the P5 core for desktop systems.
AMD K5 Architecture
As we have already said in the previous parts of the material, since its foundation, AMD has been engaged in the production of clones of Intel processors.
In the early 90s, AMD duplicates were so good that the company began to be considered as a serious player in the market.
AMD K5 Processor
Image source
At this time, AMD was already developing its first proprietary architecture.
And in 1996, the K5 platform was introduced, which was supposed to compete with the Intel Pentium.
The architecture was a RISC core, but it worked with complex CISC instructions.
This was possible due to the presence of a translator in the processor, which divided long instructions into simple RISC operations.
All K5s had five integer blocks and one floating point calculation block.
The architecture also provided for the presence of a branch prediction block, the size of which was four times larger than that of the Pentium.
The size of the instruction cache was 16 Kbytes, and the data was 8 Kbytes.
The clock frequency of the processors ranged from 75 MHz to 133 MHz.
Despite the fact that the architecture was superior to the Pentium in many characteristics, in practice the K5 processors were inferior to Intel solutions and were not widely used.
Intel P6 Architecture
In 1995, the P5 architecture was replaced, you will never believe it, by the P6 architecture — a CISC platform with a RISC core.
To divide complex operations into simple ones, the processors had a special decoder.
P6 was superscalar and supported changes in the order of operations.
Its conveyor had as many as 12 stages.
The architecture also provided a branch prediction block.
The processors used a dual independent bus, which significantly increased the memory bandwidth.
P6 had the most productive floating point computing unit at that time.
In the same year, 1995, the next generation Pentium Pro processors were introduced.
The crystals operated at a frequency of 150-200 MHz, had 16 KB of first level cache and up to 1 MB of second level cache.
It should be noted that the Pentium Pro did not support the MMX instruction set.
Largely because of this, the chips were inferior in performance to Pentium processors in 16 bit applications.
In the desktop segment, the Pentium Pro frankly failed, and soon Intel "retrained" them into server ones.
And for ordinary users, the Pentium II was introduced in 1997.
The second generation of "stumps" was based on the same P6 core (codenamed Klamath), which was used in Pentium Pro processors.
Compared to the Pentium, the second generation of crystals has increased the cache memory of the first level to 32 Kbytes.
MMX instructions were also added.
Given the poor performance of the Pentium Pro in 16 bit applications, changes were made to the architecture with an eye just for everyday work.
As a result, the performance in 16 bit programs increased by a third.
The maximum frequency of Klamath processors was 300 MHz.
Intel Pentium Pro Processor
Image source
In 1998, processors with an improved P6 core (Deschutes) appeared on sale.
They became less hot.
At the same time, the frequency potential of the models has increased.
So, Deschutes could work at a frequency of 450 MHz.
By the way, for the first time there was a differentiation in the Pentium II line: server and Low End processors began to be sold under separate brands: Xeon and Celeron, respectively.
In 1999, the first Pentium III processors were introduced.
They were based on a new generation of the P6 core called Katmai, which were modified versions of Deschutes.
Support for SSE instructions was added to the kernel, and the mechanism for working with memory was improved.
The clock frequency of Katmai processors reached 600 MHz.
Intel Pentium III processor
Image source
At the end of 1999, the core of Coppermine replaced Katmai.
The new processors were produced according to the 180 nm process technology and had an integrated second level cache memory.
unlike Katmai, where it was taken out of the processor.
The frequency of the processors has already reached 1.13 GHz.
AMD K6 Architecture
After the failure of the K5 architecture, AMD was determined to create a worthy competitor to Intel processors.
The company took a non standard path — in 1996, the company acquired a small developer of x86 processors NexGen and released their Nx686 project as K6.
The new architecture was seriously different from the K5.
The K6 processors supported changing the order of execution of instructions, the MMX instruction set and the floating point calculation block.
Like K5, the new platform was a superscalar CISC architecture with a RISC core.
The first K5 processors were produced using 350 nm and 250 nm process technology, had 64 KB of first level cache memory and operated at frequencies scattered in the range of 166-300 MHz.
In 1998, AMD released "stones" with an improved K6-2 architecture.
The new crystals competed with the most productive models of the Pentium II.
The processors received support for the 3DNow!
SIMD instruction set, which improved performance in floating point calculations, as well as a first level cache increased to 64 KB.
The maximum frequency of the chip was 550 MHz.
K6-2 was a commercially successful architecture that provided AMD with much needed financial stability for its continued existence.
AMD K6-2 processor
Image source
In 1999, the third generation of the K6 architecture was released — K6 III.
Processors were considered as a competitor to the Pentium III.
AMD solutions really provided the same level of performance at a lower cost.
The very essence of the K6 III architecture was simple.
So, the crystal kept all the "chips" of K6-2, but at the same time it received a built in cache memory of the second level with a volume of 256 Kbytes.
The volume of the first level cache was 64 Kbytes.
At K6 III, the development of the K6 architecture was completed.
In the same 1999, it was replaced by the K7 platform.
Instead of a conclusion
So, we talked about what RISC processors were, and also delved into the technical details of chips produced in the 90s of the last century.
You have already noticed that a lot of interesting developments have appeared at this time.
In addition, this decade marked the beginning of a long and interesting rivalry between AMD and Intel, which continues to this day.
You will learn about how the processors produced in this century have evolved in the next, final part of the cycle.
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