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ce reviews∆elezose reviews of computer hardware
"emy: INTEL AMD processor evolution¤
Evolution of processors.
"aste 5: modernity
31.07.2014
Oleg olenchenko, info@ferra.ru
yersi¤ for печати printing
The 2000s are already modernity.
the first Athlon; not herself¤ successful¤ NetBurst architecture, mountains¤Chiyo PentiumТы for ¤Dre Prescott; for¤mentation dvuh¤nuclear processors; the superiority of the AMD K8 and numbing¤following the success of Intel Core H read all about it in the concluding part of the series.
Beheading
AMD K7 Intel NetBurst AMD K8 Intel Core and followers AMD K10 and followers " aklyuchenie
the following parts:
"age 1: 8 bit эп epoch;
"asti 2: 16 bitna эп epoch;
"ast 3: 32 bit processors in the second half of the 1980s;
"article 4: RISC architecture and industry development in the 1990s.
AMD K7
The debut of the AMD K7 architecture and Athlon processors came in August 1999.
The American company set itself more and more serious tasks, so the expectations of users from the new development were quite high, especially taking into account the information about technical characteristics leaking into the press.
≈ Long before the company released the K7 platform, AMD and Motorola entered into a partnership agreement, under which Motorola factories could be used to produce new processors.
The result of their cooperation was the technology of crystal production using copper compounds.
AMD newcomer Dirk Meyer was responsible for the development of the K7 architecture.
At that time, the future CEO of AMD had only recently joined the company.
Prior to that, he worked at DEC and was directly involved in the development of Alpha processors.
stem.
the ash pam of the "cyclones" has also undergone certain changes.
First of all, it should be noted that the processor cache consists of two levels.
"lozgi" of the 1st level is divided into blocks of instructions and data.
The volume of each module was 64 bytes, which in total gave 128 bytes.
For example, the Pentium III has a first level cache capacity of only 32 bytes.
the cache of the 2nd level memory in the K7 architecture was 512 bytes, but it worked at twice or three times less frequency than the processor itself.
This was due to the fact that the SRAM memory was taken out of the crystal.
Athlon processor, Slot A
"image stochnik¤
The first Athlon processors were based on the Pluto core, which was produced using a 250 nm process technology.
"amen" contained about 22 million transistors.
The "jtlons" with the Pluto cable were installed in the Slot A connector.
A little later, crystals were produced based on the Orion core, which was produced using a 180 nm process technology.
"that was the only difference between it and Pluto.
"The processors received interesting changes after the release of the 180 nm Thunderbird dra.
about the first, from now on, AMD products were compatible with the Socket A connector.
secondly, they have also undergone significant architectural changes.
the ash memory of the 2nd level was transferred directly to the processor draw and worked at the same frequency with it.
Despite the fact that its volume has been reduced to 256 bytes, its speed has increased.
In addition, the clock frequency of the system bus was increased.
"Now it functioned with a frequency of 133 l√ts, that is, its effective indicator is equal to л ls¤ 266 l√ts.
by the way, AMD's processors were the first to overcome the gigahertz limit.
On March 6, 2000, the Athlon Thunderbird became the first "stone" in history with an operating frequency of 1 √√ts.
But even this did not become the limit for the K7 architecture, since a little later models were developed that operated at a frequency of 1400 l / c.
√Gigahertz Athlon for the Slot A connector
"image stochnik¤
Despite the commercial and technological success of the K7, the architecture was far from perfect.
Its main problem was the slow cache of the 2nd level - even after it was moved to the crystal, its performance left much to be desired.
"also, the lack of support for the "Intel" SSE instruction set was considered a disadvantage of the first "jtlons".
These commands were a kind of analogue of the 3DNow!
instructions, and the overwhelming majority of applications were "sharpened" under SSE.
for this reason, Athlon processors were often inferior in performance to Intel crystals.
These shortcomings were fixed in the new Palomino DRE, on the basis of which the Athlon XP (eXtra Performance) solutions were released.
in addition to SSE support and a faster cache of the 2nd level, the crystals finally got a thermal sensor for temperature tracking.
the Palomino core was produced according to the 180 nm process technology, but in comparison with its predecessors it became more complicated and contained almost 38 million transistors.
Most of the Athlon XP models were installed in the Socket A connector, although there were also transitional versions for Slot A.
The maximum clock frequency of the Palomino is 1733 l√ts.
Athlon XP processor for Socket A
"image stochnik¤
Note that with the release of Athlon XP, AMD introduced a rating system for naming processors.
"ak, the index of any model from now on did not display the real clock frequency of the dra.
For example, the Athlon XP 2000+ functioned at a speed of 1667 l / c and was comparable in performance to a Pentium 4 processor with a frequency of 2000 l/c.
the Palomino core was introduced in October 2001, and after 9 months it was replaced by Thoroughbred (Tbred A) processors.
This solution is the same Palomino dro, but produced according to 130 nm technological standards.
AMD unexpectedly experienced problems with increasing the clock frequency in new processors, so after two months a new revision was made Thoroughbred — Tbred B.
According to the architectural design, Tbred A was slightly different from Tbred B, but this allowed the updatedру dru to reach a frequency of 2200 l√ts.
Thoroughbred also increased the system bus frequency to 166 l√ts.
The last advent of the K7 architecture was the Barton draw, released in 2003.
The processors differed from Thoroughbred only by the level 2 cache increased to 512 bytes.
Barton was only slightly superior in performance to Tbred B, and AMD hastened to bring its new architecture called K8 to the market.
Intel NetBurst
remembering the Intel P6 architecture, I canot say that it has finally exhausted its potential by the end of its life cycle.
it is quite possible that by making certain changes, it was possible to get more productive processors based on it.
But Intel engineers thought differently and created a completely new architecture called NetBurst, which replaced P6 in 2000.
"just like AMD K7, NetBurst was developed with the expectation of high clock speeds.
Therefore, the architecture was based on the principle of hyperconveyerization, which, roughly speaking, was an analogue of the superconveyor technology in K7.
Therefore, NetBurst processors similarly had a pipeline with a large number of stages.
the first NetBurst revisions — the Willamette and Northwood drahs had a depth of 20 stages.
later versions — Prescott and Cedar Mill could already boast of 31 stages.
- the stages of decoding instructions were not included, since the decoder itself was taken out of the pipeline.
"if earlier complex operations were decoded on the fly, then in NetBurst the splitting of instructions occurred at the stage of copying the code to the cache of the 1st level memory.
The type of Pentium 4 processors
"image stochnik¤
by the way, about the cache memory.
She was of a different type in NetBurst.
"so, the traditional memory was replaced by a cache of micro operation sequences (Trace Cache), which stores decoded instruction traces, which allowed the decoder not to re process recently performed operations.
"this approach allowed to increase the throughput of loading instructions, as well as reduce the heat dissipation of the processor.
The cache volume in NetBurst is 12 thousand micro operations.
the memory itself worked at a half time (relative to the clock) frequency.
Among other things, the design of arithmetic logic devices was changed.
јЋ " was divided into 3 blocks.
One of them was "slow J"", which works with all integer operations.
the other two are "2X јЋ"", performing only elementary operations (for example, addition).
The branch prediction block has also been finalized.
compared with the same module of the P6 architecture, the number of errors in the calculation of x was reduced by 33%.
The first draw with the NetBurst architecture, called Willamette, operated at a frequency of up to 2 √√ts with a system bus frequency of 400 √ √ts.
his worn out cycle was short lived.
Since 2002, it has been replaced by Northwood processors.
unlike the 180 nm dra Willamette, these crystals were manufactured according to the 130 nm process technology.
"they also received a cache volume of the 2nd level increased to 512 bytes and support for Hyper Threading multithreading technology.
The Northwood frequency range ranged from 1.6 √√c to 3.4 √√c.
Northwood processors supported Hyper Threading technology
"image stochnik¤
The most significant changes were received by the next draw in the line — Prescott, released in 2004.
the reproduction of processors was again transferred to more subtle technological standards — 90 nm.
But the architecture design itself has also changed.
"So, the volume of cache memory increased to 1 MB (and in the Prescott 2M revision to 2 MB), and the pipeline received 31 stages instead of 20 in Willamette and Northwood.
The branch prediction block was improved, support for SSE3 instructions was added, and a little later — a 64 bit extension of the x86 instruction set.
Despite all the improvements, Prescott processors managed to be inferior in performance to Northwood in single threaded applications at the same clock frequency.
Moreover, they had a huge power consumption and heat dissipation, which is why Prescott was awarded the well deserved title of the most powerful x86 processor.
In 2005, Intel introduced its first dual core Pentium D processor based on the Smithfield chip.
"a kind of "stump" is represented by two Prescott holes located on the same substrate.
- it turned out not to be the most successful, probably because the Pentium D had all the disadvantages of Prescott (primarily high heat dissipation).
"In order to fit into a 130 watt TDP, Intel engineers had to limit the Smithfield clock frequency to a bar of 2.8 √√ts.
“since the performance of the NetBurst architecture strongly depended on the frequency, the speed of the first two Intel processors left much to be desired.
—a significant role was played by the use of slow DDR2 memory, as well as the non optimization of most applications for working with two drams.
Pentium D — the first dual core Intel processor
"image stochnik¤
The last processors with the NetBurst architecture were the single core Cedar Mill and the two core Presler.
Cedar Mill was a complete analogue of Prescott 2M, except for the production technology — it was manufactured according to 65 nm technological standards.
the transition to the new "rails" allowed to reduce the power consumption of the dra, but to increase the clock frequencies.
"now it concerns the Presler two dern model, then in terms of design it is a repeat of Smithfield, that is, two dra were located on the same substrate, with the only difference: Cedar Mill was used instead of Prescott.
In 2008, the release of the latest processors with the NetBurst architecture was stopped.
NetBurst has been replaced by a more advanced microarchitect ra Core.
AMD K8
at the end of 2003, AMD released a new K8 architecture.
This time there were not so many architectural changes.
there were three key innovations: a 64 bit architecture, a built in memory controller and a HyperTransport bus.
AMD's new products are called the Athlon 64.
Indeed, it was in K8 crystals that the x86 architecture was first expanded and became 64 bit.
- amo extension is officially called x86 x86-64, but AMD named it in its own way — AMD64.
Backward compatibility with 16 - and 32 bit applications was also obtained, that is, 64 bit AMD processors worked with old programs without problems.
A new performance increase in comparison with the K7 was provided by the built in memory controller.
if earlier the data also passed through the north bridge, which acted as a connecting link between the processor and the memory, now the connection was made, for example.
in addition, the volume of the associative translation buffer was increased and the branch prediction block was improved.
Athlon 64 processor
"image stochnik¤
computers with the Athlon 64 chipset and other processors with the K8 architecture used the HyperTransport bus.
She worked at a frequency of 200 l√ts.
Thanks to DDR (Double Data Rate) support, it could transmit two packets at once in one clock cycle, providing a bandwidth of 3.2 √bytes/s.
the rest of the K8 innovations were rather quantitative in nature.
For example, the processor pipeline has become longer by two stages.
for integer operations, their number is 12, and for floating — point numbers 17.
The FPU block has retained the previous design.
but the cache has not changed¤.
64 bit "jtlons" supported many instruction sets, such as MMX, 3DNow!, SSE, SSE2 and SSE3.
In addition, the processors received support for Cool'n'Quiet energy saving technology and hardware protection against buffer overflow error NX bit (No Execute bit).
The first Athlon 64 models were built on a 130 nm Clawhammer and were installed in both Socket 754 (single channel operation mode"") and Socket 939 (dual channel operation mode"").
- processor ratings ranged from 2600+ to 4000+.
- the most productive Athlon 64 processors had the FX prefix
"image stochnik¤
"and Clawhammer was followed by the Newcastle draw, which had almost no differences from its predecessor.
it disabled 512 bytes of Level 2 memory cache and added support for NX Bit technology, which was absent in the first implementations of the K8 architecture.
as part of the next DRA, Winchester, released in September 2004, all processors were installed exclusively in the Socket 939 connector.
Architecturally, Winchester was no different from Newcastle.
In April 2005, AMD released the next K8 architecture draw — San Diego.
The processor received support for the SSE3 instruction set, as well as a redesigned memory controller that taught how to work with DDR 433/466/500 modules.
The maximum rating of the" stones " of San Diego is 4000+.
"The final chord in the line of single core K8 processors was the Orleans draw, introduced in the second quarter of 2006.
ristall received support for AMD V virtualization technology, but its main feature was working exclusively through the new Socket AM2 connector.
We take the cache of the 2nd level memory equal to 512 bytes, and the maximum crystal rating is 4000+.
At the same time, the level of energy consumption was limited to 62 tons, while all previous ones consumed at least 89 tons.
In 2005, AMD introduced its first dual core processors under the Athlon 64 X2 brand.
such models were based on two д dra made on a single crystal.
They had a common memory controller, a HyperTransport bus, and a command queue.
Plus, an additional management logic was located in the processor.
At the same time, the cache memory was individual for each dra.
Athlon 64 X2 competitor of the Pentium D line
"image stochnik¤
"The Athlon 64 X2 had all the "children's balls" inherent in the first dual core processors.
first, the chip area was significantly larger in comparison with single dern models.
ak and power consumption.
"Nevertheless, the TDP level was found at a completely acceptable level, especially taking into account the "voracity" of competing solutions in the face of Pentium D.
For example, the heat package of the Athlon 64 X2 3800 + processor was 89 t, while the similar indicator of the Athlon 64 3800+ model is 65 t.
secondly, in applications that did not involve multithreading, single core crystals were faster than dual core ones due to a higher clock frequency.
during 2005 and 2006, AMD released four generations of dual core chips: three 90 nm Manchester, Toledo and Windsor chips, as well as 65 nm Brisbane chips.
the processors differed in the volume of cache memory of the 2nd level and power consumption.
"For example, Brisbane had 512 bytes of cache for each draw and had a TDP of 89 tons.
The maximum rating of Brisbane was 6000+ at a frequency of 3100 l√c, hot Wind on the basis of д DRA Windsor produced an Athlon 64 X2 6400 + processor with a clock frequency of 3200 l√c.
Do not forget that the K8 architecture was the basis of solutions for other market segments — budget Sempron crystals, Opteron server and mobile Turion.
Intel Core and followers
The failure of the NetBurst architecture forced Intel to rethink its strategy for the near future.
Pentium 4 processors have shown that NetBurst cannot adequately compete with AMD K8.
even more: over time, the advantage of the competitor's solutions only increased.
Therefore, in the microarchitecture of the next generation, which received the Core and was introduced in early 2006, it was decided to return to the root and borrow the best features of the P6 architecture.
- the list of received changes should be started from the conveyor.
he received "only" 14 stages — about the same number used by the P6 pipeline, in contrast to the 31 stage design of NetBurst.
The processor has learned to process up to four instructions per clock cycle.
The Core architecture was originally designed for two dernity, so a common cache of level 2 memory was provided for all "heads".
"this approach provided more speed and less power consumption.
Core added support for various energy saving technologies, the essence of which was to enable the necessary processor logic if necessary.
The performance was also positively affected by the improved work with the memory subsystem.
In addition to all of the above, the algorithm for processing 128 bit SSE, SSE2 and SSE3 instructions was redesigned in Core.
If earlier each command was processed in two cycles, now only one cycle was required for the operation.
Note that the Core architecture differed from NetBurst by the lack of support for some technologies: for example, Hyper Threading and a Level 3 memory cache.
The Core 2 trademark has replaced the Pentium
"image stochnik¤
The debut of the Core microarchitecture was marked by processors with the code names Merom, Conroe, Allendale and Woodcrest.
"if the first and last were intended for mobile and server systems, respectively, then the second and third were aimed at the desktop segment.
the Allendale core was a stripped down version of Conroe, it reduced the frequency of the system bus from 1066 l√c to 800 l√c, and also reduced the volume of the cache memory of the 2nd level from 4 MB to 2 MB.
plus, there was no support for hardware virtualization.
These "stones" received their original names.
Intel introduced the Core 2 trademark, which replaced the Pentium in the upper and middle price segment.
The brand has remained, but the "stumps" have now migrated to the budget segment, where they live to this day.
Core marked the return of Intel to a leading position in the processor market.
compared with Pentium D crystals, Conroe's performance increased by an average of 40%, and power consumption decreased by the same 40%.
In addition, Conroe as a whole confidently outperformed the AMD Athlon 64 X2 in performance.
In 2007, the Core was replaced by the 45 nm Penryn microarchitecture.
The modifications were minimal.
in the production of new crystals, metal gates and materials with a high index of the dielectric constant began to be used.
support for SSE4 instructions was added to the architecture, and the maximum cache volume of level 2 memory for dual core processors was increased from 4 MB to 6 MB.
The Penryn generation was represented by two dern Wolfdale solutions and four dern Yorkfield.
isual comparison of Conroe and Wolfdale
"image stochnik¤
Nehalem, the next generation architecture, was released in 2008.
compared to Core and Penryn, it has received many improvements.
ak and AMD K8 processors have got a built in three channel DDR3 memory controller.
Nehalem received a new modular structure, which later allowed adding a graphics draw to the processor, and in general it is easier to increase the number of holes in the chip.
The FSB bus has finally become a thing of the past — instead of it, the QPI (QuickPath Interconnect) interface was used in the older processors for the Socket LGA1366 connector, and DMI (Direct Media Interface) was used in the Socket LGA1156 solution.
The memory cache of the 2nd level was reduced to 256 bytes for each draw, but L3 support was added.
- yes, they supported SMT (Simultaneous Multithreading) technology an analog of Hyper Threading.
You can read more about Nehalem's innovations in this review.
"more than a year later, Intel transferred the Nehalem architecture to a new 32 nm process technology.
This line of processors was named Westmere.
Solutions have been released with the integrated Clarkdale graphics module, as well as the desktop top six door Gulftown models.
since then, Intel has managed to bring to the market 32 nm processors of the next generation — Sandy Bridge and their 22 nm modification Ivy Bridge.
last year, crystals based on the 22 nm Haswell architecture were on sale.
AMD K10 and its followers
— With the introduction of the Intel Core architecture, AMD found itself in a rather difficult situation.
If at the time of the competition of its K8 platform with the "Intel" NetBurst, the advantage of the first was obvious, now everything was exactly the opposite.
even the top end K8 processors hardly held back the onslaught of not the fastest Conroe, so AMD hastened to release the architecture of the new generation K10.
The positive thing for AMD was that the K8 itself was a successful product and it did not need to be radically redesigned.
"nevertheless, the changes affected almost all processor blocks, and this does not count as a general optimization of the architecture of the dra.
If earlier only two dra could be located on one crystal, now this number has increased to six.
in addition to the cache of the 1st and 2nd levels, the K10 models finally received L3 "brains" with a volume of 2 MB.
It was shared.
At the same time, the volume of the data and instructions cache of the 1st level is 64 bytes each, and the memory cache of the 2nd level is 512 bytes.
Another difference from the K8 was the memory controller.
processors used one 128 — bit controller, and in K10 there were two of them 64 bit.
in many ways, the change in the architecture of the controller was caused by the multiplicity of processors.
by the way, each memory controller has received its own buffer.
"this approach made it possible to reduce delays when contacting the client.
The development also affected the FPU blocks.
each processor draw had a 128 bit floating point computing module.
The algorithms for predicting transitions have been improved.
as a result, the K10 architecture has learned to process two 128 bit SSE instructions per clock cycle.
in addition, the new processors worked through the HyperTransport 3.0 interface.
Compared with previous versions, the new generation of buses provided a higher data exchange rate due to a higher clock frequency (up to 2.6 √√ts).
The efficiency of crystals began to play a big role, so in K10 AMD worked on various energy saving technologies (Cool'n'Quiet 2.0, CoolCore), which allowed turning off idle processor blocks or automatically reducing the frequency of unloaded cores.
The trade mark Phenom has replaced Athlon
"image stochnik¤
The first processors with the K10 architecture were Opteron server solutions, released in 2007.
The K10 desktop models received the name "Phenom".
They replaced the "cyclones", but AMD retained the trademark for its Low End products.
The first solutions based on K10 were made according to the aging 65 nm process technology.
unfortunately, the AMD architecture could not oppose much to a competitor in the face of Intel Core.
at the end of 2008, K10 switched to 45 nm technorms.
in the new version of the architecture (10.5), the memory controller was trained to work with DDR2 and DDR3 memory, and power consumption was significantly reduced, which significantly increased the clock speeds of the processors.
the desktop segment received Phenom II processors, which were installed in the new Socket AM3 connector, which, however, retained backward compatibility with the previous Socket AM2+.
in terms of performance, the K10.
5 managed to reduce the huge gap from Intel Core.
the previous production "moved" from 45 nm to 32 nm process technology.
However, such crystals found their application only in the first APU (Accelerated Processing Unit) of AMD, codenamed Llano.
Two bit AMD Phenom II X6 processor
"image stochnik¤
¬ In 2011, the K10 was replaced by a fundamentally new Bulldozer architecture.
The main difference between the "Bulldozer" and the previous platforms was in the very structure of the core (or rather the module).
Each module contained two cores, each of which had its own block of integer calculations and a cache memory of the 1st level. .
At the same time, within the framework of one module, there was a common block of floating point calculations, 2 MB of L2 cache and a device for fetching and decoding instructions.
In terms of work, the "building block" was similar to Intel Hyper Threading technology — we can even say that the ideas of the "Intel" technology were implemented here at the hardware level.
At the same time, in terms of performance, the Bulldozer module was approaching a full fledged dual core processor, with almost half as many transistors.
Thanks to the redesigned architecture, Bulldozer could boast of executing four instructions per clock cycle.
- Among other improvements, it is necessary to note the support of the cache of the 3rd level with a volume of 8 MB, the HyperTransport 3.1 bus, the technology of increasing the frequency of the second generation Turbo Core and the AVX, SSE 4.1, SSE 4.2, AES instruction sets.
"also, Bulldozer processors were endowed with a dual channel DDR3 memory controller with an effective frequency of 1866 l√ts.
AMD Bulldozer Processor
"image stochnik¤
The first solutions based on Bulldozer were FX crystals.
But they were never able to push Intel processors.
AMD quickly realized the critical situation, so soon (in mid 2013) the next generation of processors was born — Piledriver.
The model is an improved Bulldozer architecture in all respects.
The branch prediction blocks have been improved, the performance of floating point operations and integer calculations has increased, as well as the clock frequency.
- tal faster integrated memory controller.
At the same time, energy consumption and heat generation decreased.
on average, processors with the Piledriver architecture have become 15% faster than "bulldozers".
More detailed information about the results of these processors can be found in our review of the AMD FX 8350.
Well, earlier this year, AMD introduced the third generation of the Bulldozer architecture the Steamroller platform.
It has not undergone any drastic changes in comparison with Piledriver.
—the most significant innovation is the integration of each module with its own independent decoder, which can process up to four instructions per clock cycle.
The operation of the cache memory, the branch prediction block and the memory controller has been improved.
"an exception
this is why our story about the history of the development of central processors has come to an end.
a few years ago, you can see how modern "stones" differ from those solutions that were produced 15-20 years ago.
"it's amazing how they can even have common features at the same time.
For example, the same x86 architecture.
j And as for the near future, we will certainly have a lot of interesting things waiting for us.
At the end of this year, the release of the 14 nm Intel Broadwell architecture is planned, and the new Skylake platform is planned for the second half of 2015.
AMD is ready to release the latest generation of Bulldozer architecture called Excavator next year, after which it is planned to launch completely new crystals.
It is clear that Intel and AMD will not let us get bored.
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